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MCP631/2/3/5
24 MHz, 2.5 mA Op Amps
Features
* * * * * * * * Gain Bandwidth Product: 24 MHz (typical) Short Circuit Current: 70 mA (typical) Noise: 10 nV/Hz (typical, at 1 MHz) Rail-to-Rail Output Slew Rate: 10 V/s (typical) Supply Current: 2.5 mA (typical) Power Supply: 2.5V to 5.5V Extended Temperature Range: -40C to +125C
Description
The Microchip Technology, Inc. MCP631/2/3/5 family of operational amplifiers features high gain bandwidth product (24 MHz, typical) and high output short circuit current (70 mA, typical). Some also provide a Chip Select pin (CS) that supports a low power mode of operation. These amplifiers are optimized for high speed, low noise and distortion, single-supply operation with rail-to-rail output and an input that includes the negative rail. This family is offered in single (MCP631), single with CS pin (MCP633), dual (MCP632) and dual with two CS pins (MCP635). All devices are fully specified from -40C to +125C.
Typical Applications
* * * * Driving A/D Converters Power Amplifier Control Loops Barcode Scanners Optical Detector Amplifier
Typical Application Circuit
VDD/2 VIN R1 R3 MCP63X Power Driver with High Gain R2 VOUT RL
Design Aids
* * * * * * SPICE Macro Models FilterLab(R) Software MindiTM Circuit Designer & Simulator Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes
Package Types
MCP631 SOIC
NC 1 VIN- 2 VIN+ 3 VSS 4 8 NC 7 VDD 6 VOUT 5 NC
MCP632 SOIC
VOUTA 1 VINA- 2 VINA+ 3 VSS 4 8 VDD 7 VOUTB 6 VINB- 5 VINB+
MCP633 SOIC
NC 1 VIN- 2 VIN+ 3 VSS 4 8 CS 7 VDD 6 VOUT 5 NC
MCP635 MSOP
VOUTA 1 VINA- 2 VINA+ 3 VSS 4 CSA 5 10 VDD 9 VOUTB 8 VINB- 7 VINB+ 6 CSB
MCP632 3x3 DFN *
VOUTA 1 VINA- 2 VINA+ 3 VSS 4 8 VDD 7 VOUTB 6 VINB- 5 VINB+ VOUTA VINA- VINA+ VSS CSA
1 2 3 4 5
MCP635 3x3 DFN *
10 VDD
9 8 7 6
VOUTB VINB- VINB+ CSB
* Includes Exposed Thermal Pad (EP); see Table 3-1.
(c) 2009 Microchip Technology Inc.
DS22197A-page 1
MCP631/2/3/5
NOTES:
DS22197A-page 2
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
1.0
1.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
VDD - VSS .......................................................................6.5V Current at Input Pins ....................................................2 mA Analog Inputs (VIN+ and VIN-) . VSS - 1.0V to VDD + 1.0V All other Inputs and Outputs .......... VSS - 0.3V to VDD + 0.3V Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ..........................150 mA Storage Temperature ...................................-65C to +150C Max. Junction Temperature ........................................ +150C ESD protection on all pins (HBM, MM) ................ 1 kV, 200V
Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See Section 4.1.2 "Input Voltage and Current Limits".
1.2
Specifications
DC ELECTRICAL SPECIFICATIONS
TABLE 1-1:
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL and CS = VSS (refer to Figure 1-2).
Parameters
Input Offset Input Offset Voltage Input Offset Voltage Drift Power Supply Rejection Ratio Input Current and Impedance Input Bias Current Across Temperature Across Temperature Input Offset Current Common Mode Input Impedance Differential Input Impedance Common Mode Common-Mode Input Voltage Range Common-Mode Rejection Ratio Open Loop Gain DC Open Loop Gain (large signal) Output Maximum Output Voltage Swing
Sym
VOS VOS/TA PSRR IB IB IB IOS ZCM ZDIFF VCMR CMRR CMRR AOL AOL VOL, VOH VOL, VOH
Min
-8 -- 61 -- -- -- -- -- -- VSS - 0.3 63 66 88 94 VSS + 20 VSS + 40 40 35 2.5 1.2
Typ
1.8 2.0 76 4 100 1500 2 10 ||9 1013||2 -- 78 81 115 124 -- -- 85 70 -- 2.5
13
Max
+8 -- -- -- -- 5,000 -- -- -- VDD - 1.3 -- -- -- -- VDD - 20 VDD - 40 130 110 5.5 3.6
Units Conditions
mV V/C TA= -40C to +125C dB pA pA pA pA ||pF ||pF V dB dB dB dB mV mV mA mA V mA No Load Current (Note 1) VDD = 2.5V, VCM = -0.3 to 1.2V VDD = 5.5V, VCM = -0.3 to 4.2V VDD = 2.5V, VOUT = 0.3V to 2.2V VDD = 5.5V, VOUT = 0.3V to 5.2V VDD = 2.5V, G = +2, 0.5V Input Overdrive VDD = 5.5V, G = +2, 0.5V Input Overdrive VDD = 2.5V (Note 2) VDD = 5.5V (Note 2) TA= +85C TA= +125C
Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: 2:
ISC ISC VDD IQ
See Figure 2-5 for temperature effects. The ISC specifications are for design guidance only; they are not tested.
(c) 2009 Microchip Technology Inc.
DS22197A-page 3
MCP631/2/3/5
TABLE 1-2: AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS (refer to Figure 1-2).
Parameters
AC Response Gain Bandwidth Product Phase Margin Open Loop Output Impedance AC Distortion Total Harmonic Distortion plus Noise Step Response Rise Time, 10% to 90% Slew Rate Noise Input Noise Voltage Input Noise Voltage Density Input Noise Current Density
Sym
GBWP PM ROUT THD+N
Min
-- -- -- --
Typ
24 65 20 0.0015
Max
-- -- -- --
Units
MHz % G = +1
Conditions
G = +1, VOUT = 2VP-P, f = 1 kHz, VDD = 5.5V, BW = 80 kHz G = +1, VOUT = 100 mVP-P G = +1 f = 0.1 Hz to 10 Hz
tr SR Eni eni ini
-- -- -- --
20 10 16 10 4
-- -- -- -- --
ns V/s VP-P
nV/Hz f = 1 MHz fA/Hz f = 1 kHz
TABLE 1-3:
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS (refer to Figure 1-1 and Figure 1-2).
Parameters
CS Low Specifications CS Logic Threshold, Low CS Input Current, Low CS High Specifications CS Logic Threshold, High CS Input Current, High GND Current CS Internal Pull Down Resistor Amplifier Output Leakage CS Dynamic Specifications CS Input Hysteresis CS High to Amplifier Off Time (output goes High-Z) CS Low to Amplifier On Time
Sym
Min
Typ
Max
Units
Conditions
VIL ICSL VIH ICSH ISS RPD IO(LEAK) VHYST tOFF tON
VSS --
-- 0.1
0.2VDD --
V nA CS = 0V
0.8VDD -- -2 -- -- -- -- -- 0.7 -1 5 50
VDD -- -- -- -- -- -- 10
V A A M nA CS = VDD, TA = +125C CS = VDD
0.25 200 2
V ns s G = +1 V/V, VL = VSS CS = 0.8VDD to VOUT = 0.1(VDD/2) G = +1 V/V, VL = VSS, CS = 0.2VDD to VOUT = 0.9(VDD/2)
DS22197A-page 4
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
TABLE 1-4: TEMPERATURE SPECIFICATIONS
Sym
TA TA TA JA JA JA JA Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND.
Parameters Temperature Ranges
Specified Temperature Range Operating Temperature Range Storage Temperature Range
Min
-40 -40 -65 -- -- -- --
Typ
-- -- -- 60 149.5 57 202
Max
+125 +125 +150 -- -- -- --
Units
C C C C/W C/W C/W C/W (Note 2) (Note 2) (Note 1)
Conditions
Thermal Package Resistances
Thermal Resistance, 8L-3x3 DFN Thermal Resistance, 8L-SOIC Thermal Resistance, 10L-3x3 DFN Thermal Resistance, 10L-MSOP Note 1: 2:
Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150C). Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias.
1.3
Timing Diagram
0.1 nA (typical) VIL tON VOUT High-Z On -2.5 mA (typical) VIH tOFF High-Z -1 A (typical)
EQUATION 1-1:
G DM = R F R G G N = 1 + G DM V CM = V P ( 1 - 1 G N ) + V REF ( 1 G N ) V OST = V IN- - V IN+ V OUT = V REF + ( V P - V M )G DM + V OST G N Where: GDM = Differential Mode Gain GN = Noise Gain VCM = Op Amp's Common Mode Input Voltage VOST = Op Amp's Total Input Offset Voltage (V/V) (V/V) (V) (mV)
ICS CS
0.7 A (typical)
0.7 A (typical)
-1 A ISS (typical)
FIGURE 1-1:
Timing Diagram.
CF 6.8 pF RG 10 k VP VIN+ MCP63X VIN- VM RG 10 k RF 10 k CF 6.8 pF RL 2 k VOUT CL 50 pF CB1 100 nF RF 10 k
1.4
Test Circuits
The circuit used for most DC and AC tests is shown in Figure 1-2. It independently sets VCM and VOUT; see Equation 1-1. The circuit's common mode voltage is (VP + VM)/2, not VCM. VOST includes VOS plus the effects of temperature, CMRR, PSRR and AOL.
VREF = VDD/2 VDD CB2 2.2 F
VL
FIGURE 1-2: AC and DC Test Circuit for Most Specifications.
(c) 2009 Microchip Technology Inc.
DS22197A-page 5
MCP631/2/3/5
NOTES:
DS22197A-page 6
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS.
2.1
14% Percentage of Occurrences 12% 10% 8% 6% 4% 2% 0%
DC Signal Inputs
396 Samples TA = +25C VDD = 2.5V and 5.5V
-1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 -2.4 -2.6 -2.8 -3.0
Representative Part
Input Offset Voltage (mV)
VDD = 2.5V
VDD = 5.5V
-6 -5 -4 -3 -2 -1 0 1 2 3 Input Offset Voltage (mV)
4
5
6
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4: Output Voltage.
0.0 Low Input Common Mode Headroom (V) -0.1 -0.2 -0.3 -0.4 -0.5 -50 -25
Input Offset Voltage vs.
16% Percentage of Occurrences 14% 12% 10% 8% 6% 4% 2% 0%
398 Samples VDD = 2.5V and 5.5V TA = -40C to +125C
1 Lot Low (VCMR_L - VSS)
VDD = 2.5V and 5.5V
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 Input Offset Voltage Drift (V/C)
0 25 50 75 100 Ambient Temperature (C)
125
FIGURE 2-2:
Input Offset Voltage Drift.
FIGURE 2-5: Low Input Common Mode Voltage Headroom vs. Ambient Temperature.
1.3 High Input Common Mode Headroom (V) 1.2 1.1 1.0
VDD = 5.5V VDD = 2.5V 1 Lot High (VDD - VCMR_H)
-2.0 -2.2 -2.4 -2.6 -2.8 -3.0 -3.2 -3.4 -3.6 -3.8 -4.0
Input Offset Voltage (mV)
Representative Part VCM = VSS
+125C +85C +25C -40C
0.9 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V) -50 -25 0 25 50 75 100 Ambient Temperature (C) 125
FIGURE 2-3: Input Offset Voltage vs. Power Supply Voltage with VCM = 0V.
(c) 2009 Microchip Technology Inc.
FIGURE 2-6: High Input Common Mode Voltage Headroom vs. Ambient Temperature.
DS22197A-page 7
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS.
2.0 Input Offset Voltage (mV) 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 -0.5 3.0 1.0 2.5 0.0 0.5 1.5 2.0 Input Common Mode Voltage (V)
DC Open-Loop Gain (dB)
VDD = 2.5V Representative Part +125C +85C +25C -40C
130 125 120 115 110 105 100 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
VDD = 5.5V
VDD = 2.5V
FIGURE 2-7: Input Offset Voltage vs. Common Mode Voltage with VDD = 2.5V.
2.0 Input Offset Voltage (mV) 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 2.0 -0.5 6.0 0.0 0.5 1.0 1.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Common Mode Voltage (V)
VDD = 5.5V Representative Part +125C +85C +25C -40C
FIGURE 2-10: DC Open-Loop Gain vs. Ambient Temperature.
130 DC Open-Loop Gain (dB) 125 120 115 110 105 100 95 100 1.E+02 1k 10k 1.E+03 1.E+04 Load Resistance () 100k 1.E+05
VDD = 2.5V VDD = 5.5V
FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V.
110 105 100 95 90 85 80 75 70 65 60 -50 -25
FIGURE 2-11: Load Resistance.
1.E-08 10n Input Bias, Offset Currents (pA) 1n 1.E-09 100p 1.E-10 10p 1.E-11
VDD = 5.5V VCM = VCMR_H
DC Open-Loop Gain vs.
CMRR, PSRR (dB)
CMRR, VDD = 2.5V CMRR, VDD = 5.5V
IB
PSRR
| IOS |
1p 1.E-12 25 45 65 85 105 Ambient Temperature (C) 125
0 25 50 75 Ambient Temperature (C)
100
125
FIGURE 2-9: CMRR and PSRR vs. Ambient Temperature.
FIGURE 2-12: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V.
DS22197A-page 8
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS.
1.E-03 1m Input Current Magnitude (A) 100 1.E-04 10 1.E-05 1 1.E-06 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12
+125C +85C +25C -40C
2000 Input Bias, Offset Currents (pA) 1500 1000 500 0 -500 -1000 -1500 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Representative Part TA = +125C VDD = 5.5V
IB
IOS
4.0
4.5
5.0
5.5
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-13: Input Bias Current vs. Input Voltage (below VSS).
FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125C.
200 Input Bias, Offset Currents (pA) 150 100 50 0 -50 -100 -150 -200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Common Mode Input Voltage (V) 5.5
Representative Part TA = +85C VDD = 5.5V IOS IB
FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85C.
(c) 2009 Microchip Technology Inc.
DS22197A-page 9
6.0
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS.
2.2
Other DC Voltages and Currents
1000 3.5
VDD = 5.5V
Output Voltage Headroom (mV)
3.0 Supply Current (mA/amplifier) 2.5 2.0 1.5 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 6.0 5.5 100 Power Supply Voltage (V) 6.5 6.0
+125C +85C +25C -40C
100
VOL - VSS VDD = 2.5V
10
VDD - VOH
1 0.1 1 10 Output Current Magnitude (mA)
FIGURE 2-16: Output Voltage Headroom vs. Output Current.
20 18 16 14 12 10 8 6 4 2 0
FIGURE 2-19: Supply Voltage.
3.5 3.0 Supply Current (mA/amplifier) 2.5 2.0 1.5 1.0 0.5
Supply Current vs. Power
RL = 2 k
Output Headroom (mV)
VDD = 5.5V
VDD = 5.5V
VOL - VSS
VDD = 2.5V
VDD = 2.5V
VDD - VOH
0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 100 125 -0.5 Common Mode Input Voltage (V) 4.5
-50
-25
0 25 50 75 Ambient Temperature (C)
FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature.
100 80 60 40 20 0 -20 -40 -60 -80 -100 0.0 0.5 1.0 1.5 2.0 2.5
FIGURE 2-20: Supply Current vs. Common Mode Input Voltage.
Output Short Circuit Current (mA)
+125C +85C +25C -40C
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Power Supply Voltage (V)
FIGURE 2-18: Output Short Circuit Current vs. Power Supply Voltage.
6.5
DS22197A-page 10
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS.
2.3
100
Frequency Response
36 Gain Bandwidth Product (MHz) 34 32 30 28 26 24 22 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1k 1.E+3 100k 1.E+5 Frequency (Hz) 10k 1.E+4 1M 1.E+6 10M 1.E+7 -0.5 Common Mode Input Voltage (V) 6.0 80
PM GBWP PM
80 75 65 60 55 50 45 40 Phase Margin () Phase Margin () 70
VDD = 5.5V VDD = 2.5V
90 CMRR, PSRR (dB) 80 70 60 50 40 30 20 10 100 1.E+2
CMRR PSRR+ PSRR-
FIGURE 2-21: Frequency.
CMRR and PSRR vs.
FIGURE 2-24: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage.
36 Gain Bandwidth Product (MHz) 34 32 30 28 26 24 22 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V)
GBWP
140 120 Open-Loop Gain (dB) 100 80 60 40 20 0 -20
| AOL |
0 -30
AOL
75 70
VDD = 5.5V VDD = 2.5V
-60 -90 -120 -150 -180 -210 -240
Open-Loop Phase ()
65 60 55 50 45 40
1 10 100 1k 10k 1.E+5 1M 1.E+7 1.E+8 1.E+0 1.E+1 1.E+2 1.E+3 1.E+4 100k 1.E+6 10M 100M Frequency (Hz)
FIGURE 2-22: Frequency.
36 Gain Bandwidth Product (MHz) 34 32 30 28 26 24 22 20 -50 -25
VDD = 5.5V VDD = 2.5V
Open-Loop Gain vs.
FIGURE 2-25: Gain Bandwidth Product and Phase Margin vs. Output Voltage.
80 75 Phase Margin () 70 65 60 55 50 45
Closed-Loop Output Impedance () 100
G = 101 V/V G = 11 V/V G = 1 V/V
PM
10
1
GBWP
0 25 50 75 100 Ambient Temperature (C)
40 125
0.1 10k 1.0E+04
100k 1.0E+05
1M 10M 1.0E+06 1.0E+07 Frequency (Hz)
100M 1.0E+08
FIGURE 2-23: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature.
FIGURE 2-26: Closed-Loop Output Impedance vs. Frequency.
(c) 2009 Microchip Technology Inc.
DS22197A-page 11
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS.
10 9 7 6 5 4 3 2 1 0 10p 1.0E-11 100p 1n 1.0E-10 1.0E-09 Normalized Capacitive Load; CL/GN (F)
GN = 1 V/V GN = 2 V/V GN 4 V/V
Channel-to-Channel Separation; RTI (dB)
Gain Peaking (dB)
8
150 140 130 120 110 100 90 80 70 RS = 10 k 60 RS = 100 k 50 1k 10k 1.E+03 1.E+04
RS = 0 RS = 100 RS = 1 k
VCM = VDD/2 G = +1 V/V
100k 1M 1.E+05 1.E+06 Frequency (Hz)
10M 1.E+07
FIGURE 2-27: Gain Peaking vs. Normalized Capacitive Load.
FIGURE 2-28: Channel-to-Channel Separation vs. Frequency.
DS22197A-page 12
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS.
2.4
Input Noise Voltage Density (V/Hz)
1.E+4 10
Noise and Distortion
20 Input Noise; e ni(t) (V) 15 10 5 0 -5 -10 -15 -20
1 1.E+0 10 1.E+1 100 1.E+2 Frequency (Hz) 1k 1.E+3 10k 1.E+4 100k 1.E+6 1.E+7 1M 10M 1.E+5
Analog NPBW = 0.1 Hz Sample Rate = 2 SPS VOS = -3150 V Representative Part
1.E+3 1
100n 1.E+2
10n 1.E+1
1n 1.E+0 0.1 1.E-1
0
5 10 15 20 25 30 35 40 45 50 55 60 65 Time (min)
FIGURE 2-29: vs. Frequency.
200 180 160 140 120 100 80 60 40 20 0
Input Noise Voltage Density
FIGURE 2-32: 0.1 Hz Filter.
1
Input Noise vs. Time with
Input Noise Voltage Density (nV/Hz)
VDD = 2.5V
THD + Noise (%)
0.1
BW = 22 Hz to > 500 kHz G = 1 V/V G = 11 V/V
VDD = 5.5V
0.01
0.001
BW = 22 Hz to 80 kHz VDD = 5.0V VOUT = 2 VP-P
f = 100 Hz
-0.5
0.0001 100 1.E+2
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
1k 1.E+3
Common Mode Input Voltage (V)
10k 1.E+4 Frequency (Hz)
100k 1.E+5
FIGURE 2-30: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 100 Hz.
20 18 16 14 12 10 8 6 4 2 0
FIGURE 2-33:
THD+N vs. Frequency.
Input Noise Voltage Density (nV/Hz)
VDD = 2.5V
VDD = 5.5V
f = 1 MHz
0.5
3.0
-0.5
Common Mode Input Voltage (V)
FIGURE 2-31: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 1 MHz.
(c) 2009 Microchip Technology Inc.
5.5
0.0
1.0
1.5
2.5
3.5
4.0
5.0
2.0
4.5
DS22197A-page 13
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS.
2.5
Time Response
VDD = 5.5V G=1
VIN
VOUT
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
Output Voltage (10 mV/div)
Output Voltage (V)
VDD = 5.5V G = -1 RF = 1 k VIN
VOUT
0.0
0.1
0.2
0.3
0.4 0.5 Time (s)
0.6
0.7
0.8
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Time (s)
FIGURE 2-34: Step Response.
5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
Non-inverting Small Signal
FIGURE 2-37: Response.
7 Input, Output Voltages (V) 6 5 4 3 2 1 0 -1 0 1 2 3
Inverting Large Signal Step
VDD = 5.5V G=1
VDD = 5.5V G=2 VOUT VIN
Output Voltage (V)
VIN
VOUT
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Time (s)
4 5 6 Time (ms)
7
8
9
10
FIGURE 2-35: Step Response.
Non-inverting Large Signal
FIGURE 2-38: The MCP631/2/3/5 family shows no input phase reversal with overdrive.
24 22 20 18 16 14 12 10 8 6 4 2 0
Output Voltage (10 mV/div)
VIN
Falling Edge VDD = 5.5V VDD = 2.5V
VDD = 5.5V G = -1 RF = 1 k
Slew Rate (V/s)
VOUT
Rising Edge
0.0
0.1
0.2
0.3
0.4 0.5 Time (s)
0.6
0.7
0.8
-50
-25
0 25 50 75 Ambient Temperature (C)
100
125
FIGURE 2-36: Response.
Inverting Small Signal Step
FIGURE 2-39: Temperature.
Slew Rate vs. Ambient
DS22197A-page 14
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS.
10 Maximum Output Voltage Swing (V P-P )
VDD = 5.5V VDD = 2.5V
1
0.1 100k 1.E+05
1M 10M 1.E+06 1.E+07 Frequency (Hz)
100M 1.E+08
FIGURE 2-40: Maximum Output Voltage Swing vs. Frequency.
(c) 2009 Microchip Technology Inc.
DS22197A-page 15
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS.
2.6
1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0
Chip Select Response
CS = VDD
0.40 0.35 CS Hysteresis (V) 0.30 0.25 0.20 0.15 0.10 0.05 0.00
VDD = 2.5V VDD = 5.5V
CS Current (A)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V)
-50
-25
0 25 50 75 Ambient Temperature (C)
100
125
FIGURE 2-41: Supply Voltage.
3.0 2.5 CS, V OUT (V) 2.0 1.5 1.0 0.5 0.0 -0.5 0 2 4
Off CS
CS Current vs. Power
FIGURE 2-44: Temperature.
5 CS Turn On Time (s) 4 3 2 1 0
CS Hysteresis vs. Ambient
VDD = 2.5V G=1 VL = 0V
VDD = 2.5V
VOUT On
Off
VDD = 5.5V
6
8 10 12 Time (s)
14
16
18
20
-50
-25
0 25 50 75 Ambient Temperature (C)
100
125
FIGURE 2-42: CS and Output Voltages vs. Time with VDD = 2.5V.
6 5 CS, V OUT (V) 4 3 2 1 0 -1 0 2 4 6 8 10 12 Time (s) 14 16 18 20
Off On VOUT CS VDD = 5.5V G=1 VL = 0V
FIGURE 2-45: CS Turn On Time vs. Ambient Temperature.
8 CS Pull-down Resistor (M) 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 Ambient Temperature (C) 100 125
Representative Part
Off
FIGURE 2-43: CS and Output Voltages vs. Time with VDD = 5.5V.
FIGURE 2-46: CS's Pull-down Resistor (RPD) vs. Ambient Temperature.
DS22197A-page 16
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
Note: Unless otherwise indicated, TA = +25C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CS = VSS.
0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 0.0 0.5 1.0 1.5 1.E-06 1 Output Leakage Current (A) 1.E-07 100n 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Output Voltage (V)
+25C +125C +85C
CS = VDD
CS = VDD = 5.5V
Negative Power Supply Current; I SS (A)
-40C +25C +85C +125C
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Power Supply Voltage (V)
FIGURE 2-47: Quiescent Current in Shutdown vs. Power Supply Voltage.
6.5
FIGURE 2-48: Output Voltage.
Output Leakage Current vs.
(c) 2009 Microchip Technology Inc.
DS22197A-page 17
MCP631/2/3/5
NOTES:
DS22197A-page 18
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP631 SOIC 6 2 3 4 -- -- -- -- -- 7 1,5,8 --
PIN FUNCTION TABLE
MCP632 SOIC 1 2 3 4 -- -- 5 6 7 8 -- -- DFN 1 2 3 4 -- -- 5 6 7 8 -- 9 MCP633 SOIC 6 2 3 4 8 -- -- -- -- 7 1,5 -- MCP635 MSOP 1 2 3 4 5 6 7 8 9 10 -- -- DFN 1 2 3 4 5 6 7 8 9 10 -- 11 Symbol VOUT, VOUTA VIN-, VINA- VIN+, VINA+ VSS CS, CSA CSB VINB+ VINB- VOUTB VDD NC EP Description Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Negative Power Supply Chip Select Digital Input (op amp A) Chip Select Digital Input (op amp B) Non-inverting Input (op amp B) Inverting Input (op amp B) Output (op amp B) Positive Power Supply No Internal Connection Exposed Thermal Pad (EP); must be connected to VSS
3.1
Analog Outputs
3.4
Chip Select Digital Input (CS)
The analog output pins (VOUT) are low-impedance voltage sources.
This input (CS) is a CMOS, Schmitt-triggered input that places the part into a low power mode of operation.
3.2
Analog Inputs
3.5
Exposed Thermal Pad (EP)
The non-inverting and inverting inputs (VIN+, VIN-, ...) are high-impedance CMOS inputs with low bias currents.
There is an internal connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). This pad can be connected to a PCB ground plane to provide a larger heat sink. This improves the package thermal resistance (JA).
3.3
Power Supply Pins
The positive power supply (VDD) is 2.5V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors.
(c) 2009 Microchip Technology Inc.
DS22197A-page 19
MCP631/2/3/5
NOTES:
DS22197A-page 20
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
4.0 APPLICATIONS
VDD D1 R1 D2 MCP63X VOUT R2 VSS - (minimum expected V1) 2 mA VSS - (minimum expected V2) R2 > 2 mA R1 > The MCP631/2/3/5 family op amps is manufactured using Microchip's state of the art CMOS process. It is designed for low cost, low power and high speed applications. Its low supply voltage, low quiescent current and wide bandwidth make the MCP631/2/3/5 ideal for battery-powered applications.
V1 V2
4.1
4.1.1
Input
PHASE REVERSAL
The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-38 shows an input voltage exceeding both supplies with no phase inversion.
4.1.2
INPUT VOLTAGE AND CURRENT LIMITS
FIGURE 4-2: Inputs.
Protecting the Analog
The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. VDD Bond Pad
It is also possible to connect the diodes to the left of the resistor R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN-) should be very small. A significant amount of current can flow out of the inputs (through the ESD diodes) when the common mode voltage (VCM) is below ground (VSS); see Figure 2-13. Applications that are high impedance may need to limit the usable voltage range.
4.1.3
NORMAL OPERATION
VIN+ Bond Pad
Input Stage
Bond V - IN Pad
The input stage of the MCP631/2/3/5 op amps uses a differential PMOS input stage. It operates at low common mode input voltages (VCM), with VCM between VSS - 0.3V and VDD - 1.3V. To ensure proper operation, the input offset voltage (VOS) is measured at both VCM = VSS - 0.3V and VDD - 1.3V. See Figure 2-5 and Figure 2-6 for temperature effects. When operating at very low non-inverting gains, the output voltage is limited at the top by the VCM range (< VDD - 1.3V); see Figure 4-3.
VSS Bond Pad
FIGURE 4-1: Structures.
Simplified Analog Input ESD
VIN
VDD MCP63X VOUT
In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see Section 1.1 "Absolute Maximum Ratings "). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN-) from going too far above VDD, and dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2.
V SS < V IN, V OUT V DD - 1.3V
FIGURE 4-3: Unity Gain Voltage Limitations for Linear Operation.
(c) 2009 Microchip Technology Inc.
DS22197A-page 21
MCP631/2/3/5
4.2
4.2.1
Rail-to-Rail Output
MAXIMUM OUTPUT VOLTAGE
VDD IDD IOUT VOUT RSER VL IL RL VLG
The Maximum Output Voltage (see Figure 2-16 and Figure 2-17) describes the output range for a given load. For instance, the output voltage swings to within 50 mV of the negative rail with a 1 k load tied to VDD/2.
MCP63X ISS VSS
4.2.2
OUTPUT CURRENT
Figure 4-4 shows the possible combinations of output voltage (VOUT) and output current (IOUT), when VDD = 5.5V. IOUT is positive when it flows out of the op amp into the external circuit.
6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5
FIGURE 4-5: Calculations.
Diagram for Power
The instantaneous op amp power (POA(t)), RSER power (PRSER(t)) and load power (PL(t)) are:
(VDD = 5.5V) RL = 1 k
VOH Limited
EQUATION 4-2:
+ISC Limited
-ISC Limited
RL = 100 RL = 10
VOUT (V)
POA(t) = IDD (VDD - VOUT) + ISS (VSS - VOUT) PRSER(t) = IOUT2RSER PL(t) = IL2RL The maximum op amp power, for resistive loads, occurs when VOUT is halfway between VDD and VLG or halfway between VSS and VLG:
VOL Limited
-80
-60
-40
-20
0
20
40
60
80
100
-120
-100
IOUT (mA)
120
FIGURE 4-4: 4.2.3
Output Current.
EQUATION 4-3: POAmax max2(VDD - VLG , VLG - VSS) 4(RSER + RL)
POWER DISSIPATION
Since the output short circuit current (ISC) is specified at 70 mA (typical), these op amps are capable of both delivering and dissipating significant power. Figure 4-5 show the quantities used in the following power calculations for a single op amp. RSER is 0 in most applications; it can be used to limit IOUT. VOUT is the op amp's output voltage, VL is the voltage at the load, and VLG is the load's ground point. VSS is usually ground (0V). The input currents are assumed to be negligible. The currents shown are approximately:
The maximum ambient to junction temperature rise (TJA) and junction temperature (TJ) can be calculated using POAmax, ambient temperature (TA), the package thermal resistance (JA) found in Table 1-4, and the number of op amps in the package (assuming equal power dissipations):
EQUATION 4-4:
EQUATION 4-1:
IOUT = IL = VOUT - VLG RSER + RL Where: n
TJA = POA(t) JA n POAmaxJA TJ = TA + TJA
= number of op amps in package (1, 2)
IDD IQ + max(0, IOUT) ISS -IQ + min(0, IOUT) Where: IQ = quiescent supply current
DS22197A-page 22
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
The power de-rating across temperature for an op amp in a particular package can be easily calculated (assuming equal power dissipations): Figure 4-7 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
1,000 Recommended R ISO ()
EQUATION 4-5: T - TA POAmax Jmax n JA
Where:
TJmax = absolute maximum junction temperature
Several techniques are available to reduce TJA for a given POAmax: * Lower JA - Use another package - PCB layout (ground plane, etc.) - Heat sinks and air flow * Reduce POAmax - Increase RL - Limit IOUT (using RSER) - Decrease VDD
100
GN = +1 GN +2
10 10p 1.E-12
100p 1n 1.E-11 1.E-10 1.E-09 Normalized Capacitance; CL/GN (F)
10n 1.E-08
FIGURE 4-7: Recommended RISO Values for Capacitive Loads.
After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP631/2/3/5 SPICE macro model are helpful.
4.3
4.3.1
Improving Stability
CAPACITIVE LOADS
Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 20 pF when G = +1), a small series resistor at the output (RISO in Figure 4-6) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. RG RF RISO VOUT CL RN MCP63X
4.3.2
GAIN PEAKING
Figure 4-8 shows an op amp circuit that represents non-inverting amplifiers (VM is a DC voltage and VP is the input) or inverting amplifiers (VP is a DC voltage and VM is the input). The capacitances CN and CG represent the total capacitance at the input pins; they include the op amp's common mode input capacitance (CCM), board parasitic capacitance and any capacitor placed in parallel.
VP VM
RN
CN MCP63X VOUT
RG
CG
RF
FIGURE 4-8: Capacitance.
Amplifier with Parasitic
FIGURE 4-6: Output Resistor, RISO stabilizes large capacitive loads.
CG acts in parallel with RG (except for a gain of +1 V/V), which causes an increase in gain at high frequencies. CG also reduces the phase margin of the feedback loop, which becomes less stable. This effect can be reduced by either reducing CG or RF.
(c) 2009 Microchip Technology Inc.
DS22197A-page 23
MCP631/2/3/5
CN and RN form a low-pass filter that affects the signal at VP. This filter has a single real pole at 1/(2RNCN). The largest value of RF that should be used depends on noise gain (see GN in Section 4.3.1 "Capacitive Loads"), CG and the open-loop gain's phase shift. Figure 4-9 shows the maximum recommended RF for several CG values. Some applications may modify these values to reduce either output loading or gain peaking (step response overshoot).
1.E+05 100k
4.4
MCP633 and MCP635 Chip Select
F
Maximum Recommended R ()
10k 1.E+04
CG = 10 pF CG = 32 pF CG = 100 pF CG = 320 pF CG = 1 nF
The MCP633 is a single amplifier with Chip Select (CS). When CS is pulled high, the supply current drops to 1 A (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. The CS pin has an internal 5 M (typical) pulldown resistor connected to VSS, so it will go low if the CS pin is left floating. Figure 1-1, Figure 2-42 and Figure 2-43 show the output voltage and supply current response to a CS pulse. The MCP635 is a dual amplifier with two CS pins; CSA controls op amp A and CSB controls op amp B. These op amps are controlled independently, with an enabled quiescent current (IQ) of 2.5 mA/amplifier (typical) and a disabled IQ of 1 A/amplifier (typical). The IQ seen at the supply pins is the sum of the two op amps' IQ; the typical value for the MCP635's IQ will be 2 A, 2.5 mA or 5 mA when there are 0, 1 or 2 amplifiers enabled, respectively.
1k 1.E+03
100 1.E+02 1 10 Noise Gain; GN (V/V)
GN > +1 V/V
100
4.5
Power Supply
FIGURE 4-9: RF vs. Gain.
Maximum Recommended
Figure 2-34 and Figure 2-35 show the small signal and large signal step responses at G = +1 V/V. The unity gain buffer usually has RF = 0 and RG open. Figure 2-36 and Figure 2-37 show the small signal and large signal step responses at G = -1 V/V. Since the noise gain is 2 V/V and CG 10 pF, the resistors were chosen to be RF = RG = 1 k and RN = 500. It is also possible to add a capacitor (CF) in parallel with RF to compensate for the de-stabilizing effect of CG. This makes it possible to use larger values of RF. The conditions for stability are summarized in Equation 4-6.
With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high frequency performance. Surface mount, multilayer ceramic capacitors, or their equivalent, should be used. These op amps require a bulk capacitor (i.e., 2.2 F or larger) within 50 mm to provide large, slow currents. Tantalum capacitors, or their equivalent, may be a good choice. This bulk capacitor can be shared with other nearby analog parts as long as crosstalk through the supplies does not prove to be a problem.
4.6
High Speed PCB Layout
EQUATION 4-6:
Given: G N1 = 1 + R F R G
G N2 = 1 + C G C F
f Z = f F ( G N1 G N2 ) We need: f F f GBWP ( 2G N2 ) , G N1 < G N2 f F f GBWP ( 4G N1 ) , G N1 > G N2
f F = 1 ( 2R F C F )
These op amps are fast enough that a little extra care in the PCB (Printed Circuit Board) layout can make a significant difference in performance. Good PC board layout techniques will help you achieve the performance shown in the specifications and Typical Performance Curves; it will also help you minimize EMC (Electro-Magnetic Compatibility) issues. Use a solid ground plane. Connect the bypass local capacitor(s) to this plane with minimal length traces. This cuts down inductive and capacitive crosstalk. Separate digital from analog, low speed from high speed, and low power from high power. This will reduce interference. Keep sensitive traces short and straight. Separate them from interfering components and traces. This is especially important for high frequency (low rise time) signals.
DS22197A-page 24
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
Sometimes, it helps to place guard traces next to victim traces. They should be on both sides of the victim trace, and as close as possible. Connect guard traces to ground plane at both ends, and in the middle for long traces. Use coax cables, or low inductance wiring, to route signal and power to and from the PCB. Mutual and self inductance of power wires is often a cause of crosstalk and unusual behavior.
4.7.3
H-BRIDGE DRIVER
Figure 4-12 shows the MCP632 dual op amp used as a H-bridge driver. The load could be a speaker or a DC motor. 1/2 MCP632
VIN
4.7
4.7.1
Typical Applications
POWER DRIVER WITH HIGH GAIN
RF RGT RGB
RF
VOT RL
Figure 4-10 shows a power driver with high gain (1 + R2/R1). The MCP631/2/3/5 op amp's short circuit current makes it possible to drive significant loads. The calibrated input offset voltage supports accurate response at high gains. R3 should be small, and equal to R1||R2, in order to minimize the bias current induced offset. R1 R3 VIN R2
RF
VOB
VDD/2
1/2 MCP632
FIGURE 4-12:
H-Bridge Driver.
VDD/2
VOUT RL MCP63X
This circuit automatically makes the noise gains (GN) equal, when the gains are set properly, so that the frequency responses match well (in magnitude and in phase). Equation 4-7 shows how to calculate RGT and RGB so that both op amps have the same DC gains; GDM needs to be selected first.
FIGURE 4-10: 4.7.2
Power Driver.
EQUATION 4-7:
V OT - V OB G DM -------------------------------- 1 V/V V IN - V DD 2 RF R GT = -------------------------------( G DM 2 ) - 1 RF R GB = -----------------G DM 2 Equation 4-8 gives the resulting common mode and differential mode output voltages.
OPTICAL DETECTOR AMPLIFIER
Figure 4-11 shows a transimpedance amplifier, using the MCP63X op amp, in a photo detector circuit. The photo detector is a capacitive current source. RF provides enough gain to produce 10 mV at VOUT. CF stabilizes the gain and limits the transimpedance bandwidth to about 1.1 MHz. RF's parasitic capacitance (e.g., 0.2 pF for a 0805 SMD) acts in parallel with CF. CF 1.5 pF Photo Detector ID 100 nA CD 30pF MCP63X VDD/2 RF 100 k
EQUATION 4-8:
V OT + V OB V DD -------------------------- = ---------2 2 VOUT V DD V OT - V OB = G DM V IN - ---------- 2
FIGURE 4-11: Transimpedance Amplifier for an Optical Detector.
(c) 2009 Microchip Technology Inc.
DS22197A-page 25
MCP631/2/3/5
NOTES:
DS22197A-page 26
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
5.0 DESIGN AIDS
5.5
Microchip provides the basic design aids needed for the MCP631/2/3/5 family of op amps.
Analog Demonstration and Evaluation Boards
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP631/2/3/5 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves.
Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help customers achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site at www.microchip.com/analog tools. Some boards that are especially useful are: * * * * * * MCP6XXX Amplifier Evaluation Board 1 MCP6XXX Amplifier Evaluation Board 2 MCP6XXX Amplifier Evaluation Board 3 MCP6XXX Amplifier Evaluation Board 4 Active Filter Demo Board Kit 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV
5.2
FilterLab(R) Software
Microchip's FilterLab(R) software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the Filter-Lab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance.
5.6
Application Notes
The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. * ADN003: "Select the Right Operational Amplifier for your Filtering Circuits", DS21821 * AN722: "Operational Amplifier Topologies and DC Specifications", DS00722 * AN723: "Operational Amplifier AC Specifications and Applications", DS00723 * AN884: "Driving Capacitive Loads With Op Amps", DS00884 * AN990: "Analog Sensor Conditioning Circuits - An Overview", DS00990 * AN1228: "Op Amp Precision Design: Random Noise", DS01228 Some of these application notes, and others, are listed in the design guide: * "Signal Chain Design Guide", DS21825
5.3
MindiTM Circuit Designer & Simulator
Microchip's MindiTM Circuit Designer & Simulator aids in the design of various circuits useful for active filter, amplifier and power management applications. It is a free online circuit designer & simulator available from the Microchip web site at www.microchip.com/mindi. This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, and simulate circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation.
5.4
Microchip Advanced Part Selector (MAPS)
MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/maps, the MAPS is an overall selection tool for Microchip's product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase and Sampling of Microchip parts.
(c) 2009 Microchip Technology Inc.
DS22197A-page 27
MCP631/2/3/5
NOTES:
DS22197A-page 28
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN (3x3) (MCP632) Device MCP632
Note:
Example
Code DABM
Applies to 8-Lead 3x3 DFN
XXXX YYWW NNN
DABM 0931 256
8-Lead SOIC (150 mil) (MCP631, MCP632, MCP633) XXXXXXXX XXXXYYWW NNN
Example:
MCP631E SN e3 0931 256
10-Lead DFN (3x3) (MCP635)
Example
Code BAFB
Applies to 10-Lead 3x3 DFN
XXXX YYWW NNN
Device MCP635
Note:
BAFB 0931 256
10-Lead MSOP (MCP635)
Example:
XXXXXX YWWNNN
635EUN 931256
Legend: XX...X Y YY WW NNN *e3 Note:
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. e3
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2009 Microchip Technology Inc.
DS22197A-page 29
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DS22197A-page 32
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DS22197A-page 33
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DS22197A-page 35
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DS22197A-page 36
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
APPENDIX A: REVISION HISTORY
Revision A (August 2009)
* Original Release of this Document.
(c) 2009 Microchip Technology Inc.
DS22197A-page 37
MCP631/2/3/5
NOTES:
DS22197A-page 38
(c) 2009 Microchip Technology Inc.
MCP631/2/3/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X Temperature Range
MCP631 MCP631T MCP632 MCP632T MCP633 MCP633T MCP635 MCP635T
/XX Package
Examples:
a) MCP631T-E/SN: Tape and Reel Extended temperature, 8LD SOIC package MCP632T-E/MF: Tape and Reel Extended temperature, 8LD DFN package MCP632T-E/SN: Tape and Reel Extended temperature, 8LD SOIC package MCP633T-E/SN: Tape and Reel Extended temperature, 8LD SOIC package MCP635T-E/MF: Tape and Reel Extended temperature, 10LD DFN package MCP635T-E/UN: Tape and Reel Extended temperature, 10LD MSOP package
Device:
Single Op Amp Single Op Amp (Tape and Reel) (SOIC) Dual Op Amp Dual Op Amp (Tape and Reel) (DFN and SOIC) Single Op Amp with CS Single Op Amp with CS (Tape and Reel) (SOIC) Dual Op Amp with CS Dual Op Amp with CS (Tape and Reel) (DFN and MSOP)
a) b)
a)
a) b)
Temperature Range: E Package:
= -40C to +125C
MF = Plastic Dual Flat, No Lead (3x3 DFN), 8-lead, 10-lead SN = Plastic Small Outline (3.90 mm), 8-lead UN = Plastic Micro Small Outline (MSOP), 10-lead
(c) 2009 Microchip Technology Inc.
DS22197A-page 39
MCP631/2/3/5
NOTES:
DS22197A-page 40
(c) 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
(c) 2009 Microchip Technology Inc.
DS22197A-page 41
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4080 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
03/26/09
DS22197A-page 42
(c) 2009 Microchip Technology Inc.

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